View XRT82L24AIV_5259871.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com ? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator august 2004 rev. 1.1.2 general description the xrt82l24a is a fully integrated quad (four chan- nels) short-haul line interface unit for e1(2.048mbps) 75 w or 120 w applications. each channel consists of a receiver with equalizer for reliable data and clock re- covery, and a transmitter which accepts either single or dual-rail digital inputs for signal transmission to the line using a low output impedance line driver. the de- vice also includes a crystal-less jitter attenuator which, depending on system requirements, can be selected in the receive or transmit path through the host or hardware mode control. xrt82l24a is a low power cmos device operating on a single 3.3v supply with 5v tolerant digital inputs. features ? fully integrated quad, short-haul pcm transceivers for e1 applications. ? on chip receive equalizer and transmit pulse shaper for cept 75 w and 120 w line terminations ? on chip clock recovery circuit ? transformer or capacitor coupled receiver inputs ? crystal-less jitter attenuator can be selected in the transmit or receive path ? high receiver interference immunity ? per-channel transmit power shutdown ? tri-state transmit output capability ? on chip per-channel driver failure monitoring circuit ? on chip hdb3/b8zs/ami encoder/decoder func- tions ? supports gapped clock for multiplexer mapper applications ? transmit return loss meets or exceeds etsi 300 166 standard ? meets or exceeds specifications in itu g.703, g.775, g.736 and g.823; etsi 300-166 ? meets or exceeds g.783 and g.823 jitter specifi- cations ? 3.3v or 5.0v logic level inputs ? single +3.3v supply operation ? new patent# 6,313,671b1 low power ic i/o buffer applications ? digital cross connects (dsx-1) ? channel banks ? high speed data transmission line cards ? e1 multiplexer ? public switching systems and pbx interfaces f igure 1. b lock d iagram of the xrt82l24a e1 liu (h ost m ode ) hdb3 encoder mux tx/rx jitter attenuator tx timing control tx pulse shaper mux line driver tx/rx jitter attenuator timing & data recovery peak detector & slicer rx equalizer los detect hdb3 decoder clock generator mclk tvdd_n ttip_n tring_n tgnd_n enable/ disable rtip_n rring_n remote loopback local analog loopback digital loopback driver monitor channel 0 channel 1 channel 2 channel 3 hw/host m m m m p controller & hardware interface add [0:3] d[0:7] wr_r/w/txoff_0 ale_as/txoff_2 cs/txoff_3 rd_ds/txoff_1 test txclk_n/rzdata_n txpos_n/tdata_n txneg_n rxclk_n rxpos_n/rdata_n rxneg_n/lcv_n rxlos_n int rdy_dtack pclk/codes pts1/clke pts2/sr_dr reset ict
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 2 f igure 2. b lock d iagram of the xrt82l24a t1/e1/j liu (h ardware m ode ) txclk_n/rzdata txpos _n/tdata_n txneg_n rxclk_n rxpos_n/rdata_n rxneg_n/lcv_n rxlos_n hdb3 encoder mux tx/rx jitter attenuator tx timing control tx pulse shaper mux line driver tx/rx jitter attenuator timing & data recovery peak detector & slicer rx equalizer los detect hdb3 decoder clock generator mclk tvdd_n ttip_n tring_n tgnd_n enable/ disable rtip_n rring_n remote loopback local analog loopback digital loopback driver monitor one of four channels m m m m p controler & hardware interface add[0] add[1] add[2] add[3]/rxmute d[0]/fifos d[1]/loopen_0 d[2]/loopen_1 d[3]/loopen_2 d[4]loopen_3 d[5]/loopsel d[6]/rxja d[7]txja int rdy_dtack pclk/codes pts1/clke pts2/sr/dr reset wr_r/w/txoff0 ale_as/txoff2 cs/txoff3 rd_ds/txoff1 hw/host test ict
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 3 ordering information p art n umber p ackage o perating t emperature r ange XRT82L24AIV 100 lead tqfp (14 x 14 x 1.4mm) -40 c to +85 c f igure 3. p in o ut of the xrt82l24a rxclk_3/rzdata_3 rxlos_3 txneg_3 txpos_3/tdata_3 txclk_3 a[0] a[1] a[2] a[3]/rxmute mclk gnd vdd d[0]/fifos d[1]/loopen_0 d[2]/loopen_1 d[3]/loopen_2 d[4]/loopen_3 d[5]/loopsel d[6]/rxja d[7]/txja txclk_2 txpos_2/tdata_2 txneg_2 rxlos_2 rxclk_2/rzdata_2 rxclk_0/rzdata_0 rxlos_0 txneg_0 txpos_0/tdata_0 txclk_0 reset pts1/clke pts2/sr/dr hw/host pclk/codes agnd avdd dgnd wr_r/w/txoff_0 rd_ds/txoff_1 ale_as/txoff_2 cs/txoff_3 rdy_dtack int ict txclk_1 txpos_1/tdata_1 txneg_1 rxlos_1 rxclk_1/rzdata_1 rxpos_0/rdata_0 rxneg_0/lcv_0 dvdd dgnd agnd rring_0 rtip_0 avdd tgnd_0 tring_0 tvdd_0 ttip_0 vdd ttip_3 tvdd_3 tring_3 tgnd_3 avdd rtip_3 rring_3 agnd dgnd dvdd rxneg_3/lcv_3 rxpos_3/rdata_3 rxpos_1/rxdata_1 rxneg_1/lcv_1 dvdd dgnd dgnd rring_1 rtip_1 dvdd tgnd_1 tring_1 tvdd_1 ttip_1 agnd ttip_2 tvdd_2 tring_2 tgnd_2 avdd rtip_2 rring_2 agnd dgnd(pll) dvdd(pll) rxneg_2/lcv_2 rxpos_2/rdata_2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 50 100 76 75 51 100 lead tqfp
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 i table of contents general description ................................................................................................. 1 f eatures .............................................................................................................................. ...................... 1 a pplications .............................................................................................................................. ................ 1 figure 1. block diagram of the xrt82l24a e1 liu (host mode) ......................................................... 1 figure 2. block diagram of the xrt82l24a t1/e1/j liu (hardware mode) ........................................ 2 figure 3. pin out of the xrt82l24a ............................................................................................ ........... 3 table of contents ....................................................................................................... i pin description ............................................................................................................. 4 r eceiver s ections .............................................................................................................................. ...... 4 t ransmitter s ections .............................................................................................................................. 4 m icroprocessor i nterface ...................................................................................................................... 5 c locks .............................................................................................................................. ......................... 7 j itter a ttenuator .............................................................................................................................. ...... 7 c ontrol .............................................................................................................................. ....................... 7 p ower s upplies and g rounds ................................................................................................................. 8 system-functional description ......................................................................... 10 r eceiver .............................................................................................................................. .................... 10 j itter a ttenuator .............................................................................................................................. .... 10 g apped c lock (ja m ust be e nabled in the t ransmit p ath ) ................................................................. 10 t able 1: m aximum g ap w idth for m ultiplexer /m apper a pplications ............................................... 10 hdb3/ami d ecoder .............................................................................................................................. ... 10 r eceiver l oss of s ignal (los) .............................................................................................................. 10 c onditions for declaring and clearing los in the e1 m ode . ............................................................ 11 r eceive d ata m uting .............................................................................................................................. 11 loop-back modes ............................................................................................................... ............... 11 r emote l oop -b ack (rloop) mode ...................................................................................................... 11 d igital l ocal loop -b ack (dloop) mode ............................................................................................... 11 a nalog local l oop -b ack (aloop) mode .............................................................................................. 12 figure 4. remote loop-back with jitter attenuator selected in receive path .................................... 12 figure 5. remote loop-back with jitter attenuator selected in transmit path .................................. 12 figure 6. digital local loop-back with option to transmit all ones to the line (ja selected & in re- ceive path) ................................................................................................................... ........... 13 figure 7. digital local loop-back with option to transmit all ones to the line (ja selected & in transmit path) ................................................................................................................ ......... 13 figure 8. analog local loop-back signal flow jitter attenuator selected & in receive path ........ 14 figure 9. analog local loop-back signal flow jitter attenuator selected & in transmit path ........ 14 r eset o peration .............................................................................................................................. ....... 14 r eceiver m odes of o peration ............................................................................................................... 14 r eceive d ata i nvert m ode ..................................................................................................................... 14 figure 10. data changes on rising edge of clk and data is sampled on falling edge ..................... 15 figure 11. data changes on falling edge of clk and is sampled on rising edge .............................. 15 t ransmit c lock s ampling e dge ............................................................................................................. 15 single rail , d ual rail .............................................................................................................................. 15 t ransmit a ll o nes (taos) ..................................................................................................................... 1 5 hdb3/ami e ncoder .............................................................................................................................. ... 15 t ransmit p ulse s haper .......................................................................................................................... 16 d river m onitor .............................................................................................................................. ......... 16 transmit off control ............................................................................................................................ 1 6 i nterfacing the xrt 82l24a to the l ine .............................................................................................. 16 figure 12. xrt 82l24a channel 1in an e1 unbalanced 75 w application ........................................ 16 figure 13. xrt 82l24a channel 1 - e1 120 w balanced application ................................................. 17 t able 2: e1 r eceiver e lectrical c haracteristics ............................................................................. 18
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 ii t able 3: e1 t ransmitter e lectrical c haracteristics ....................................................................... 19 t able 4: t ransmit p ulse m ask s pecification ...................................................................................... 19 figure 14. itu g.703 e1 pulse template ........................................................................................ ...... 20 t able 5: dc e lectrical c haracteristics ............................................................................................ 20 t able 6: p ower c onsumption (t a =-40c to 85c, v dd =3.3v + 5%, unless otherwise specified .) .. 21 absolute maximum ratings ................................................................................... 21 t able 7: ac e lectrical c haracteristics ............................................................................................ 21 figure 15. transmit clock and input data timing .............................................................................. 22 figure 16. receive clock and output data timing. ............................................................................ 2 2 t able 8: m icroprocessor interface signal ........................................................................................ 23 t able 9: m icroprocessor r egister m ap ............................................................................................. 24 t able 10: c ommand c ontrol r egister 0 ............................................................................................. 25 t able 11: c ommand c ontrol r egister 1 ............................................................................................. 26 t able 12: c hannel s tatus r egister .................................................................................................... 27 t able 13: c hannel m ask r egister ....................................................................................................... 28 t able 14: c hannel c ontrol r egister ................................................................................................ 29 figure 17. intel interface timing (read) ...................................................................................... ......... 30 figure 18. intel interface timing (write) ..................................................................................... .......... 30 t able 15: i ntel i nterface t iming s pecifications ................................................................................. 31 figure 19. microprocessor interface timing - motorola type programmed i/o read operation ... 32 figure 20. microprocessor interface timing - motorola type programmed i/o write operation ... 32 figure 21. microprocessor interface timing - reset pulse width ..................................................... 33 t able 16: m otorola i nterface t iming s pecification .......................................................................... 33 j itter t olerance .............................................................................................................................. ...... 34 figure 22. receive maximum jitter tolerance ................................................................................... . 34 figure 23. receiver jitter transfer function (jitter attenuator disabled) ........................................ 35 figure 24. jitter attenuation function ........................................................................................ ......... 35 o rdering i nformation ............................................................................................................................ 3 6 p ackage d imensions 100 l ead tqfp 14 x 14 mm ..................................................................................... 36 r evision h istory .............................................................................................................................. ....... 37
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 4 pin description pin description s p in #n ame t ype d escription receiver sections 1 25 51 75 rxclk_0/rzdata_0 rxclk_1/rzdata_1 rxclk_2/rzdata_2 rxclk_3/rzdata_3 o receiver_n clock output rzdata output: in data slicer mode, (register 0, bit 7 = 1) or in hardware mode when mclk is absent, this signal is or-ed rzdata after the slicers. 2 24 52 74 rxlos_0 rxlos_1 rxlos_2 rxlos_3 o receiver_n loss of signal . this signal is asserted "high" to indicate loss of signal at the receive input. 100 26 50 76 rxpos_0/rdata_0 rxpos_1/rdata_1 rxpos_2/rdata_2 rxpos_3/rdata_3 o receiver 1 positive data output: in dual-rail mode, this signal is the receive p-rail output data. receiver 1 nrz data output: in single-rail mode, this signal is the receive output data. 99 27 49 77 rxneg_0/lcv_0 rxneg_1/lcv_1 rxneg_2/lcv_2 rxneg_3/lcv_3 o receiver_n negative data output: in dual-rail mode, n-rail data are sent to the framer. line code violation output - channel_n: in single-rail mode, this signal output "high" for one receive clock cycle to indi- cate a code violation is detected in the received data. if ami coding is selected, every bipolar violation received will cause this pin to go "high". 95 31 45 81 rring_0 rring_1 rring_2 rring_3 i receiver_n differential negative input. 94 32 44 82 rtip_0 rtip_1 rtip_2 rtip_3 i receiver_n differential positive input. 67 rxmute i hardware mode, receive muting : connect this pin "high" to mute rxpos/rxneg output to a low state upon receive los condition to prevent data chattering. connect low to disable mut- ing function. transmitter sections 3 23 53 73 txneg_0 txneg_1 txneg_2 txneg_3 i transmitter_n negative nrz data input . in dual-rail mode, this signal is the n- rail input data for transmitter 0. in single-rail mode, this pin can be left uncon- nected. 4 22 54 72 txpos_0/tdata_0 txpos_1/tdata_1 txpos_2/tdata_2 txpos_3/tdata_3 i transmitter_n positive data input . in dual-rail mode, this signal is the p-rail input data for transmitter 0. transmitter 0 data input . in single-rail mode, this pin is used as the nrz input data for transmitter 0.
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 5 5 21 55 71 txclk_0 txclk_1 txclk_2 txclk_3 i transmitter_n clock input: e1 rate at 2.048mhz 50ppm. during normal operation both in host mode and hardware mode, txclk is used for sampling input data at txpos / tdata and txneg , while mclk is used as the timing reference for the transmit pulse shaping circuit. if txclk is active while mclk is not present, txpos and txneg accepts nrz data input and the transmit pulse width is determined by txclk clock duty cycle. if txclk is tied to low, txpos and txneg input accepts rz data format and the pulse width is determined by the duty cycle of the input data. in rz mode, single-rail data for- mat is not supported. in hardware mode, if txclk is tied "high" for more than 10 s, then taos (a continuous all one's ami signal) will be transmitted to the line using mclk as timing reference. if txclk_0 is tied low for more than 10 s, the transmitter will be powered down and the output will be tri-stated. 14 15 16 17 txoff_0 txoff_1 txoff_2 txoff_3 i powered-down transmitter_n: in hardware mode, tie this pin "high" to power-down channel 0 transmitter and set ttip_n and tring_n to high impedance. n ote : internally pulled -up with a 50k w resistor. 91 35 41 85 tring_0 tring_1 tring_2 tring_3 o transmitter_n ring output: negative differential data output to the line. 89 37 39 87 ttip_0 ttip_1 ttip_2 ttip_3 o transmitter_n tip output: positive differential data output to the line. microprocessor interface 6 reset i hardware reset (active low). when this pin is tied low for more than 10 m s, the device is put in the reset state. n ote : internally pulled -up with a 50k w resistor. 7 pts1 clke i i processor type select bit 1: host mode in host mode the appropriate bits are set in the command mode hardware mode: the state of the clke input controls the sampling edge of both txclk and rxclk. a 1 selects the positive edge of txclk and rxclk a 0 selects the negative edge of txclk and rxclk. pin description s p in #n ame t ype d escription 8hc11,8081,80c188 (async.) motorola 68k (async.) intel x86 (sync.) intel i906,motorola 860 (sync.) pts1 0 1 0 1 pts2 0 0 1 1
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 6 8 pts2 sr/dr i host mode: processor type select input bit 2: see description for pin 7. hardware mode single rail/dual rail control connect this pin low to select transmit and receive data format in dual-rail mode. in this mode, hdb3 encoder and decoder are not available. connect this pin "high" to select single-rail data format. n ote : internally pulled -downwith a 50k w resistor. 9 hw/host i mode control input: this pin is used to select the operating mode of the device, (hardware mode or host mode.) in hardware mode , the parallel microprocessor interface is disabled and enables all hardware control pin functions. in host mode , the parallel microprocessor interface pins are used for control functions. n ote : internally pulled "high" with 50k w. 10 pclk codes i i processor clock input . input clock for synchronous microprocessor operation. maximum clock rate is 16 mhz. this pin is internally pulled-up for asynchronous microprocessor inter- face when no clock is present. coding/decoding select . in hardware mode , if single-rail data format is selected (pin 8 =1), connect this pin "high" to select ami encoding and decoding. connect this pin low to select hdb3. 14 wr _r/w i write input (read/write) . with intel bus timing, a low pulse on wr selects a write operation when cs pin is low. when configured in motorola bus timing, a "high" pulse on r/w selects a read operation and a low pulse on r/w selects a write operation when cs is low. 15 rd _ds i read input (data strobe). with intel bus timing, a low pulse on rd selects a read operation when cs pin is low. when configured in motorola bus timing, a low pulse on ds indicates a read or write operation when cs pin is low. 16 ale_as i address latch input (address strobe) . with intel bus timing, the address inputs are latched into the internal register on the falling edge of ale. when configured in motorola bus timing, the address inputs are latched into the internal register on the falling edge of as. 17 cs i chip select input . this signal must be low in order to access the parallel port. pin description s p in #n ame t ype d escription pin 9 operating mode low host mode high hardware mode
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 7 18 rdy_dtack o ready output (data transfer acknowledge output) . with intel bus timing, rdy is asserted "high" to indicate the device has com- pleted a read or write operation. when configured in motorola bus timing, dtack is asserted low to indicate the device has completed a read or write cycle. 67 68 69 70 a[3] a[2] a[1] a[0] i host mode, microprocessor interface address bus [3] host mode, microprocessor interface address bus [2] host mode, microprocessor interface address bus [1] host mode, microprocessor interface address bus [0]. 56 57 58 59 60 61 62 63 d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] i/o data bus[7:0] . microprocessor read/write data bus pins. clocks 66 mclk i master clock input . this signal is an independent 2.048mhz clock with accuracy better than 50ppm and duty cycle within 40% to 60%. the function of mclk is to provide internal timing for the pll clock recovery circuit, jitter attenuator block, refer- ence clock during transmit all ones data and timing reference for the micropro- cessor in host mode operation. if mclk is absent, all receive channels perform as analog front-end (afe). the or-ed rz data is also available at rxclk output in this mode, instead. the clock recovery function is disabled. jitter attenuator 56 txja i transmit jitter attenuator select . in hardware mode, connect this pin high to select jitter attenuator in the trans- mit path and connect low to disable jitter attenuator. setting rxja simultaneously "high" also disables jitter attenuator selection. 57 rxja i receive jitter attenuator select . in hardware mode, connect this pin high to select jitter attenuator in the receive path and connect low to disable jitter attenuator. setting txja simultaneously "high" also disables jitter attenuator selection. control 8 sr/dr i single rail/dual rail control: hardware mode connect this pin low to select transmit and receive data format in dual-rail mode. in this mode, hdb3 encoder and decoder are not available. connect this pin "high" to select single-rail data format. n ote : internally pulled -down with a 50k w resistor. 10 codes i coding/decoding select . in hardware mode , if single-rail data format is selected (pin 8 =1), connect this pin "high" to select ami encoding and decoding. connect this pin low to select hdb3. pin description s p in #n ame t ype d escription
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 8 19 int o interrupt output . this pin is asserted low to indicate an alarm condition has occurred within the device. interrupt generation can be globally disabled by setting the gie bit to a "0" in the command control register. n ote : this pin is an open drain output and requires an external 10k w pull-up resistor. 20 ict i in-circuit testing (active low) . when this pin is tied low, all output pins are forced to high impedance state for in-circuit testing. n ote : internally pulled -up with 50k w . 58 loopsel i dloop-back mode select . in hardware mode, if loopen_(0-3) is high, this pin is used for selecting loop-back mode. connect this pin "high" to select local loop-back and low to select remote loop-back. digital loop-back is not supported in hardware mode. 62 61 60 59 loopen_0 loopen_1 loopen_2 loopen_3 i loop-back enable - channel_n: in hardware mode : connect this pin high to enable channel_n loop-back operation. remote or local loop-back is determined by pin 58 setting. 63 fifos i fifo size select. in hardware mode, connect this pin "high" selects 64 bit fifo depth and con- nect low to select 32 bit fifo depth. power supplies and grounds 12 avdd **** analog positive supply(3.3v 5%) 28 dvdd **** digital positive supply(3.3v 5%) 33 dvdd **** digital positive supply(3.3v 5%) 90 36 40 86 tvdd_0 tvdd_1 tvdd_2 tvdd_3 **** transmitter_n analog positive supply(3.3v 5%). 43 avdd **** analog positive supply(3.3v 5%) 48 dvdd **** digital positive supply(3.3v 5%) 64 dvdd **** digital positive supply(3.3v 5%) 78 dvdd **** digital positive supply(3.3v 5%) 11 agnd **** analog ground 13 dgnd **** digital ground 29 dgnd **** digital ground 30 dgnd **** digital ground 92 34 42 84 tgnd_0 tgnd_1 tgnd_2 tgnd_3 **** transmitter_n analog ground. pin description s p in #n ame t ype d escription
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 9 38 agnd **** analog ground 46 agnd **** analog ground 47 dgnd **** digital ground 65 dgnd **** digital ground 79 dgnd **** digital ground 80 agnd **** analog ground 83 avdd **** analog positive supply(3.3v 5%) 88 avdd **** analog positive supply(3.3v 5%) 93 avdd **** analog positive supply(3.3v 5%) 96 agnd **** analog ground 97 dgnd **** digital ground 98 dvdd **** digital positive supply(3.3v 5%) pin description s p in #n ame t ype d escription
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 10 system-functional description a simplified single channel block diagram of the xrt 82l24a is presented in figure 1. the xrt 82l24a consists of four identical transmit and receive chan- nels for e1(2.048 mbps) pcm systems. the opera- tional mode of each channel of the line interface can be configured by the microprocessor interface (host mode) or by hardware control. receiver at the receiver input, cable attenuated ami signals can be coupled to the receiver using a capacitor or a 1:2 transformer. the receive signal first goes through the equalizer for signal conditioning before being ap- plied to the data recovery circuit. the data recovery circuit includes a peak detector which is set typically at 50% for e1 of the equalizer output peak amplitude for data slicing. after the data slicers, the digital rep- resentation of the ami signals goes to the clock re- covery circuit for timing recovery and subsequently to the hdb3 decoder (if selected) before they are output via the rxpos/rdata and rxneg/lcv pins. the digital data output can be in dual-rail or single-rail mode depending on the option selected. clock and timing recovery is accomplished by means of a digital pll scheme which can tolerate high input jitter and meets or exceeds the jitter tolerance requirements as specified in the itu - g.823 standard. jitter attenuator to reduce jitter in the transmit line signal or recovered clock and data signals, a crystal-less jitter attenuator with a 32x2 bit or 64x2 bit fifo is provided for each channel. the jitter attenuator can be configured to op- erate in either the transmit or receive path, or it can be disabled through host or hardware mode control. the jitter attenuator design is based on a digital scheme that uses the mclk signal as a reference in- put. no other high frequency clock is necessary. with the jitter attenuator selected, the typical throughput delay is 16 bits for a 32 bit fifo depth or 32 bit for a 64 bit fifo depth. the design of the jitter attenuator is such that if the write and read pointers of the fifo are within two bits of overflowing or underflowing, the bandwidth of the jitter attenuator is automatically wid- ened in order to permit the jitter attenuator pll to track the short term input jitter to avoid data corrup- tion. when this situation occurs, the jitter attenuator will not attenuate input jitter until the read/write point- er's position is outside the two bit window. under nor- mal condition, the jitter transfer characteristic meets the narrow bandwidth requirement as specified in itu- g.736 and itu- i.431standards. gapped clock (ja must be enabled in the transmit path) the xrt82l24a liu is ideal for multiplexer or mapper applications where the network data crosses multiple timing domains. as the higher data rates are de-multiplexed down to t1 or e1 data, stuffing bits are removed which can leave gaps in the incoming data stream. if the jitter attenuator is enabled in the transmit path, the 32-bit or 64-bit fifo is used to smooth the gapped clock into a steady t1 or e1 output. the maximum gap width of the xrt82l24a is shown in table 1. n ote : if the liu is used in a loop timing system, the jitter attenuator should be enabled in the receive path. hdb3/ami decoder the decoder function is only active if the chip has been configured to operate in the single-rail mode. when the single-rail mode is selected, the receive line signal will be decoded according to hdb3 rules for e1. further, any bipolar violation of the hdb3 line coding scheme will be flagged as a line code viola- tion via the lcv output pin. the lcv output pin will be pulsed high for one rxclk cycle for each line code violation that is detected. excessive number of zeros in the receive data stream are also flagged as a line code violation via the same output pin. if ami decod- ing is selected in single-rail mode operation, every bi- polar violation in the receive data stream is reported as error at the lcv pin. receiver loss of signal (los) the receiver loss of signal monitoring function is im- plemented using both analog and digital detection schemes compatible with itu g.775 requirements. when the amplitude of the e1line signal at rtip/ rring drops 16db (typical) below the 0db nominal level the digital circuit is activated to parse through and check for 32 consecutive zeros before los is as- serted, to indicate loss of input signal. the number of t able 1: m aximum g ap w idth for m ultiplexer /m apper a pplications fifo d epth m aximum g ap w idth 32-bit 20 ui 64-bit 50 ui
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 11 consecutive zeros before los is declared can be in- creased to 4096 bits. during extended los mode, the los condition will be cleared when 4096 more valid data bits are present (when operating in the host mode). the los condition is cleared when the input signal rises above 16db below 0db nominal lev- el and meets 12.5% density of 4 ones in a 32 bit win- dow with no more than 16 consecutive zeros. clock signals generated when los is declared the output signal at the rxclk output pin depends upon the type of los condition that is occurring. complete loss of signal (zero amplitude) if the xrt 82l24a experiences a complete loss of signal (e.g., no signal amplitude), then the xrt 82l24a clock recovery pll enters the training mode, and differentially begins to lock onto the signal applied to the mclk input pin. as a consequence, the clock recovery pll will begin to drive a clock signal to the terminal equipment (via the rxclk out- put pin), which is derived from the mclk input pin. degraded type of loss of signal event (non-zero amplitude) if the xrt 82l24a experiences a degraded type of los event (e.g., where there is still a small amount of discernible signal amplitude in the line signal, but small enough to qualify as an los event) then the clock recovery pll could lock onto this degraded line signal and will subsequently drive the same fre- quency via the rxclk output pins. conditions for declaring and clearing los in the e1 mode. each e1 channel of the xrt 82l24a has two criteria for los detection, analog and digital . a channel will declare a los condition when both of these los detectors detect an los condition. analog los detector the analog los detector will declare an los condi- tion, if it determines that the amplitude of the incom- ing line signal has dropped to less than -15db (below the nominal pulse amplitude of 3v for twisted-pair , or 2.37v for coaxial-cable ) for at least 32 bit-periods. the analog los detector will clear the los condi- tion, if it determines that the incoming line signal is no more than 12.5db below the nominal 3v pulse ampli- tude. n ote : the difference in the signal level required to declare and clear los is 2.5db. this 2.5db hysteresis is designed into the analog los detector circuitry, in order to prevent chattering in the los output pin or bit-field. digital los detector the digital los detector will declare an los condi- tion, if it detects a string of at least 32 consecutive "0"s. the digital los detector will clear the los condition, if it determines that the incoming e1 line signal has a pulse density of 12.5% or more without 16 consecu- tive 0s for at least 32 consecutive bit periods. n ote : the pulse density requirement of 12.5% accounts for hdb3 coding. receive data muting the xrt 82l24a permits the user to mute the re- covered data output signals anytime the los condi- tion is declared. if the user invokes this function, then the rpos/rdat and rneg output pins will be pulled to gnd for the duration that the los condition exists. this feature is useful in that it prevents the liu from routing electrical noise (which has been recovered by the clock recovery pll) to the framer ic and preventing it from declaring an los condition. this feature is enabled by setting the rxmute bit to a 1 in the host mode (register 1, bit 2 location) or by connecting pin 67 high in the hardware mode. loop-back modes each channel within the xrt 82l24a can be config- ured to operate in any of the following loop-back modes: ? remote loop-back mode ? digital local loop-back mode ? analog local loop-back mode each of these loop-back modes are described in some detail below. remote loop-back (rloop) mode with remote loop-back activated, (channel control register bit 2 = 1) in host mode or in hardware mode with loopsel (pin 58) tied low and loopen tied high received data after the jitter attenuator (if selected) is looped back to the transmit path using rxclk as transmit timing. in this mode the data/sig- nals applied to the txclk, tpos/tdat and tneg in- put pins are ignored, while rxclk and received data will continue to be available at their respective output pins. simultaneously setting rloop and aloop ac- tive is not allowed (see loop-back mode in figure 4 & figure 5). remote loop-back has priority over taos. digital local loop-back (dloop) mode the digital local loop-back mode allows the trans- mit clock and data to be looped back to the corre- sponding receiver output pins through the encoder/ decoder and the jitter attenuator. in this mode, the re- ceive line signal is ignored, but the transmit data will
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 12 be sent to the line uninterrupted. this loop back fea- ture allows users to configure the line interface as a pure jitter attenuator. (see loop-back mode in figure 6 & figure 7). n ote : digital local loop-back is not supported in hard- ware mode. analog local loop-back (aloop) mode with analog local loop-back activated, the transmit data at ttip and tring are looped-back to the ana- log input of the receiver. external inputs at rtip/ rring in this mode are ignored while valid transmit data continues to be sent to the line. analog loop- back exercises most of the functional blocks of the line interface (see loop-back mode in figure 8 & figure 9). f igure 4. r emote l oop -b ack with jitter attenuator selected in receive path tx decoder timing control rx clock & data recovery ja txpos txneg txclk rxclk rxpos rxneg encoder ttip tring rtip rring f igure 5. r emote l oop -b ack with jitter attenuator selected in transmit path tx decoder timing control rx clock & data recovery ja txpos txneg txclk rxclk rxpos rxneg encoder ttip tring rtip rring
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 13 f igure 6. d igital l ocal l oop -b ack with option to transmit all ones to the line (ja selected & in receive path ) tx decoder timing control rx clock & data recovery ja txpos txneg txclk rxclk rxpos rxneg encoder ttip tring rtip rring taos f igure 7. d igital l ocal l oop -b ack with option to transmit all ones to the line (ja selected & in transmit path ) tx decoder timing control rx clock & data recovery ja txpos txneg txclk rxclk rxpos rxneg encoder ttip tring rtip rring taos
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 14 reset operation the xrt 82l24a provides both hardware and soft- ware resets. in hardware reset, with pin 6 forced to "0" for more than 10s, the entire state of the device including the microprocessor r/w registers are reset. in software reset, only the state of the interface is re- set (the microprocessor registers are not affected). receiver modes of operation through the microprocessor interface or in hardware mode, xrt 82l24a offers several alternative receive modes of operation making it flexible for different ap- plications as dictated by the system requirements. receive data invert mode receive output data by default is active high at rx- pos/rdata and rxneg/lcv pins. these signals can be changed to active low by setting the datap bit in the interface register(register 1, bit 3 = 1). in single rail mode datap = 1, (register 0, bit 7 = 1), lcv output also becomes active low. data invert mode is only available in host mode. f igure 8. a nalog l ocal l oop -b ack signal flow j itter a ttenuator selected & in r eceive path rx clock & data recovery decoder txpos txneg txclk rxclk rxpos rxneg tx encoder timing control ttip tring rtip rring ja f igure 9. a nalog l ocal l oop -b ack signal flow j itter a ttenuator selected & in transmit path rx clock & data recovery decoder txpos txneg txclk rxclk rxpos rxneg tx encoder timing control ja ttip tring rtip rring
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 15 rxclk clock sampling edge the sampling edge of the rxclk output can be changed through control bit rclke within the inter- face register for receive output data re-timing. with rclke=1, (bit 5 = 1), data is validated on the rising edge of rxclk and with rclke=0, (bit 5 = 0),, re- ceive data is validated on the falling edge of rxclk. in hardware mode, the state of pin 7 (clke) controls the rising or falling edge of rxclk for data re-timing. transmit clock sampling edge nrz transmit data at txpos/tdata or txneg is clocked serially into the device using txclk. with the interface register bit 4 (tclke=1), input data is sam- pled on the rising edge of txclk. the sampling edge is inverted when tclke= 0. in hardware mode, the state of pin 7 (clke) controls the sampling edge of both txclk and rxclk. single rail, dual rail transmit data format can be in dual-rail (sr/dr =1) or single-rail modes (sr/dr =0). in hardware mode, du- al or single-rail format is determined by the state of pin 8. for single-rail mode operation, nrz data can be applied to txpos/tdata with txclk, while tx- neg input is left unconnected. the transmitter con- verts nrz input data into differential signal for trans- mission to the line using low impedance output driv- ers. transmit all ones (taos) in the host mode, individual channels can be pro- grammed to transmit an all ones ami signal by set- ting the per channel bit control taos=1. in this mode, input data at txpos/tdata and txneg are ignored. in host mode, reference clock for taos is txclk. if txclk is not available, mclk is used for transmis- sion. in hardware mode, if txclk is not present and high for more than 10s, taos is transmitted using mclk as a reference. remote loop-back has priori- ty over taos request. hdb3/ami encoder the encoder is only available in single-rail mode (sr/ dr =1) in host mode, or pin 8 set high in hardware mode. in an e1 system, if interface register codes=0, hdb3 encoding is selected. input data applied to txpos/tdata which contains more than four consecutive zeros will be removed and replaced by 000v or b00v, where "b indicates a pulse con- forming with bipolar rule and "v" represents a pulse violating the rule. with register codes=1, ami coding is selected. in hardware mode, hdb3 or ami coding selection is determined by the state of pin 10. f igure 10. d ata changes on rising edge of c lk and d ata is sampled on falling edge data sampled clk data data sampled f igure 11. d ata changes on falling edge of c lk and is sampled on rising edge data sampled clk data data sampled
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 16 the choice of these codes is made such that an odd number of b pulses is transmitted between consec- utive bipolar violation v pulses transmit pulse shaper the transmit pulse shaper uses high a speed clock derived from mclk to synthesize the shape and width of the transmitted pulse applied to ttip and tring. the internal high speed timing generator eliminates the need for a tightly controlled transmit clock txclk duty cycle. the intrinsic jitter at the transmit output using a jitter- free input clock source and with the jitter attenuator disabled will generate no more than 0.03uipp. driver monitor the driver monitor circuit is used for detecting trans- mit driver failure by monitoring the activity at ttip and tring. driver failure may be caused by a short- circuit in the primary of the transformer or system problems at the input. in the host mode, when the driver monitor detects no transitions at ttip and tring for more than 128 clock cycles, the dmo bit (bit 7) in the interface regis- ter is set and results in an interrupt (int ) to be gener- ated. driver monitor function is not supported in hard- ware mode. txpos/tdata and txneg polarity in host mode, transmit data at txpos/tdata and txneg can be configured for active low or active high operation, by controlling the state of the datap bit in the interface register. writing a "0" to this bit se- lects active high data and a "1" selects active low data. this control bit also selects receive output data polarity (see receive data invert mode description). this feature is not supported in hardware mode. transmit off control each transmit channel of the line interface can be shut down by writing a "1" to txoff in the channel control interface register. in the transmitter off mode, the entire transmitter is disabled and the out- puts at ttip and tring are placed in a high imped- ance state. in hardware mode, pins 14 through pin 17 are used for powering down each transmit channel independently. interfacing the xrt 82l24a to the line the xrt 82l24a in e1 configuration can be trans- former coupled to 75 w coaxial or 120 w twisted pair lines as shown in figure 12 and figure 13 below. f igure 12. xrt 82l24a c hannel 1 in an e1 unbalanced 75 w application ttip_0 tring_0 rtip_0 rring_0 txpos txneg txlineclk rxpos rxneg rxlineclk loss of signal 4 3 5 100 99 1 2 89 91 94 95 tpos_0 tneg_0 tclk_0 rpos_0 rneg_0 rclk_0 rlos_0 xrt82l24a r2 9.1 w r1 9.1 w r3 18.7 w 1 : 2 t2 t1 bnc bnc 1 4 5 8 5 8 1 4 1 : 2 1 2 1 2 coaxial cable coaxial cable
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 17 f igure 13. xrt 82l24a c hannel 1 - e1 120 w balanced application xrt82l24a ttip_0 tring_0 rtip_0 rring_0 txpos txneg txlineclk rxpos rxneg rxlineclk loss of signal 4 3 5 100 99 1 2 89 91 94 95 tpos_0 tneg_0 tclk_0 rpos_0 rneg_0 rclk_0 rlos_0 r6 9.1 w r5 9.1 w r4 30.1 w 1 : 2 t2 t1 1 4 5 8 5 8 1 4 1 : 2 ttip tring rtip rring twisted pair twisted pair
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 18 t able 2: e1 r eceiver e lectrical c haracteristics (vdd=3.3v5%, ta=-40c to 85c unless otherwise specified) p arameter m in t yp .m ax u nit t est c onditions receiver loss of signal: number of consecutive zeros before los is set - 32 - bit cable attenuation @1024khz itu-g.775, ets1 300 233 input signal level at los 15 20 - db los de-asserted 12.5 - - % ones receiver sensitivity 11 13 - db with nominal pulse amplitude of 3.0v for 120 w and 2.37v for 75 w application. with -18db interference signal added. interference margin -18 -14 - db with 6db cable loss input impedance 15 - k w jitter tolerance: 20 hz 700khz 10khz---100khz 10 5 0.3 - - - - uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude -36- 0.5 khz db itu g.736 jitter attenuator corner frequency(-3db curve) -10-hz itu g.736 return loss: 51khz --- 102khz 102khz --- 2048khz 2048khz --- 3072khz 14 20 16 - - - - - - db db db itu g.703
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 19 t able 3: e1 t ransmitter e lectrical c haracteristics (ta=-40c to 85c, vdd=3.3v5%, unless otherwise specified) p arameter m in t yp .m ax u nit t est c onditions ami output pulse amplitude: 75 w application 120 w application 2.13 2.70 2.37 3.0 2.60 3.30 v v use transformer with 1:2 ratio and 9.1 w resistor in series with each end of primary. output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 jitter added by the transmit- ter output - 0.025 0.05 uipp broad band with jitter free txclk applied to the input. return loss: 51khz --- 102khz 102khz --- 2048khz 2048khz --- 3072khz 8 14 10 - - - - - - db db db etsi 300 166 t able 4: t ransmit p ulse m ask s pecification test load impedance 75 w resistive (coax) 120 w resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 0.237v 0 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 20 f igure 14. itu g.703 e1 p ulse t emplate t able 5: dc e lectrical c haracteristics (vdd=3.3v5%, ta=25c unless otherwise specified) p arameter s ymbol m in t yp .m ax u nits power supply voltage vdd 3.13 3.3 3.46 v input high voltage v ih 2.0 - 5.0 v input low voltage v il -0.5 - 0.8 v output high voltage @ ioh=-5ma v oh 2.4 - - v output low voltage @iol=5ma v ol --0.4v input leakage current (except input pins with pull-up resistor.) i l --+ 10 a input capacitance c i - 5.0 - pf output load capacitance c l --25pf
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 21 absolute maximum ratings t able 6: p ower c onsumption (t a =-40c to 85 c, v dd =3.3v + 5%, unless otherwise specified .) p arameter s ymbol m in .t yp .m ax .u nits c onditions power consumption pc - 450 650 mw e1(75 ohm) load. at 50% mark density power consumption pc - 650 680 mw e1(75 ohm) load. at 100% mark density power consumption pc - 400 500 mw e1(120 ohm) load. at 50% mark density power consumption pc - 540 600 mw e1(120 ohm) load. at 100% mark density power consumption pc - 80 100 mw all transmitters powered-down storage temperature -65c to + 150c operating temperature -40c to + 85c supply voltage -0.5v to + 6.0v theta-ja 38 c/w theta-jc 6 c/w t able 7: ac e lectrical c haracteristics (vdd=3.3v5%, ta=25c unless otherwise specified) p arameter s ymbol m in t yp m ax u nits e1 mclk clock frequency - 2.048 - mhz mclk clock duty cycle 40 - 60 % mclk clock tolerance - 50 - ppm e1 txclk clock period t clkp - 488 - ns txclk duty cycle t cdu 30 50 70 % transmit data setup time t su 50 - - ns transmit data hold time t ho 30 - - ns txclk rise time (10%/90%) t clkr - -40ns txclk fall time (90%/10%) t clkf - -40ns rxclk duty cycle r cdu 45 50 55 % receive data setup time r su 150 - - receive data hold time r ho 150 - - ns rxclk to data delay r dy - -40ns rxclk rise time (10%/90%) with 25pf loading. r clkr --40ns rxclk fall time(90%/10%) with 25pf loading r clkf 40 ns data pulse width in data slice mode rzdata 210 244 448 ns
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 22 microprocessor interface xrt 82l24a is equipped with a microprocessor inter- face for easy device configuration. the parallel port of the xrt 82l24a is compatible with both intel and motorola address and data buses. the device has 4-bit address add[3:0] input and 8-bit bi-directional data bus add[7:0]. the signals required for a generic microprocessor to access the internal registers are described in table 8. f igure 15. t ransmit c lock and i nput d ata t iming t clkf t clkr t clkp txpos/tdata or txneg txclk data can be active high or active low. note: set tclke bit-4 "high" in command control register 0 to select txclk inversion. t ho t su f igure 16. r eceive c lock and o utput d ata t iming . r ho r su r clkf r clkr r dy rxpos or rxneg rxclk data can be active high or active low. note: set rclke bit=5 "high"in command control register 0 to select rxclk inversion.
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 23 t able 8: m icroprocessor interface signal d[7:0] data input (output): 8 bits bi-directional data bus for register access. add[3:0] address input: 4 bit address to select internal register location. pts1 pts2 processor type select: pclk process clock input: input clock for synchronous microprocessor operation. maximum clock speed is 16mhz. this pin is internally pulled up for asynchronous microprocessor operation if no clock is present. ale_as address latch input (address strobe): with intel bus timing, the address inputs are latched into the inter- nal register on the falling edge of ale. when configured in motorola bus timing, the address inputs are latched into the internal register on the falling edge of as. cs chip select input: this signal must be low in order to access the parallel port. rd _ds read input (data strobe): with intel bus timing, a low pulse on rd selects a read operation when cs pin is low. when configured in motorola bus timing, a low pulse on ds indicates a read or write operation when cs pin is low. wr _r/w write input (read/write ): with intel bus timing, a low pulse on wr selects a write operation when cs pin is low. when configured in motorola bus timing, a high pulse on r/w selects a read operation and a low pulse on r/w selects a write operation when cs pin is low. rdy_dtack ready output (data transfer acknowledge output): with intel bus timing, rdy is asserted high to indi- cate the device has completed a read or write operation. when configured in motorola bus timing, dtack is asserted low to indicate the device has completed a read or write operation. int interrupt output: this pin is asserted low to indicate an interrupt caused by an alarm condition in the device status registers. the activation of this pin can be blocked by the interrupt status register bit. 8hc11,8081,80c188 (async.) motorola 68k (async.) intel x86 (sync.) intel i906,motorola 860 (sync.) pts1 0 1 0 1 pts2 0 0 1 1
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 24 n ote : address 1110 and 1111 r/w registers (14 and 15) are reserved for exar testing purposes t able 9: m icroprocessor r egister m ap r egister n umber a ddress b it 7b it 6b it 5b it 4b it 3b it 2b it 1b it 0 command control registers (read/write ) 0 0000 sr/dr rzdata rclke tclke datap codes imask sreset 1 0001 reserved (set to 0) reserved (set to 0) fifos rxja txja rxmute exlos ict reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 channel 0 register 2 0010 dmo0 los0 lcv0 tclk0 dmo0is los0is lvc0is tckl0is 3 0011 reserved reserved reserved reserved mdmo0 mlos0 mlcv0 mtckl0 4 0100 reserved reserved reserved aloop0 dloop0 rloop0 taos0 txoff0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 channel 1 register 5 0101 dmo1 los1 lcv1 tclk1 dmo1is llosis1 lcv1 tckl1is 6 0110 reserved reserved reserved reserved mdmo1 mlos1 mlcv1 mtckl1 7 0111 reserved reserved reserved aloop1 dloop1 rloop1 taos1 txoff1 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 channel 2 register 8 1000 dmo2 los2 lvc2 tclk2 dmo2is llos2is lcv2 tckl2is 9 1001 reserved reserved reserved reserved mdmo2 mlos2 mlcv2 mtckl2 10 1010 reserved reserved reserved aloop2 dloop2 rloop2 taos2 txoff2 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 channel 3 register 11 1011 dmo3 los3 lcv3 tclk3 dmo3is llos3is lcv3 tckl3is 12 1100 reserved reserved reserved reserved mdmo3 mlos3 mlcv3 mtckl3 13 1101 reserved reserved reserved aloop3 dloop3 rloop3 taos3 txoff3 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 25 t able 10: c ommand c ontrol r egister 0 c ommand c ontrol r egister 0 p arallel p ort a ddress : 0000 b it n o .n ame f unction r egister t ype r eset v alue 7 sr/dr single/dual rail: writing a "1" to this bit selects transmit and receive data format in single-rail mode. in this mode, hdb3/b8zs/ami encoder and decoder are available. writing a "0" selects dual-rail mode. r/w 0 6rzdata rz data: writing a 1 to this bit selects receive data to pass to the output after the slicers without re-timing. in this mode, pll clock recov- ery, jitter attenuator, decoder and remote loop-back functions are disabled. r/w 0 5rclke rxclk clock edge: writing a "1" to this bit selects receive output data to be updated on positive edge of rxclk. writing a "0" to this bit selects the negative edge of rxclk. r/w 0 4tclke txclk clock edge: writing a "1" to this bit selects positive edge of txclk to sample input data. write "0" to select negative edge. r/w 0 3datap data polarity: writing a "0" to this bit selects transmit input and receive output data to be active-high. write "1" to select active-low. r/w 0 2codes coding/decoding select: this bit is used in conjunction with sr/dr bit 1. if sr/dr is "1", writing a "0" to this bit selects hdb3 coding. writing a "1" to this bit position selects ami code. r/w 0 1gie global interrupt enable: writing a "0" to this bit globally disables interrupt generation caused by any alarm generated within the line interface. write a "1" to enable interrupt generation. r/w 0 0 sreset software reset: writing a "1" to this bit longer than 10s initiates a device reset through the microprocessor interface. all internal circuits are placed in the reset state with this bit set to a "1" except the micro- processor register bits. r/w 0 n ote : register type abrbreviation: r = read only, r/w = read or write, rur = reset upon read
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 26 t able 11: c ommand c ontrol r egister 1 c ommand c ontrol r egister 1 p arallel p ort a ddress : 0001 b it n o .n ame f unction r egister t ype r eset v alue 7-- reserved must be set to 0 for proper operation. r/w 0 6-- reserved must be set to 0 for proper operation. r/w 0 5fifos fifo size select: writing a "1" to this bit selects 64 bit fifo depth. write "0" to select 32 bit fifo depth. r/w 0 4rxja receive jitter attenuator: select: writing a "1" to this bit selects jitter attenuator in the receive path. if bit 3(txja) is also set, jitter attenuator is disabled. r/w 0 3txja transmit jitter attenuator select: writing a "1" to this bit selects jitter attenuator in the transmit path. if bit 4(rxja) is also set, jitter attenuator is disabled. r/w 0 2 rxmute receive muting: writing a "1" to this bit mutes receive data output to a low state during los condition to prevent data chattering. r/w 0 1 exlos extended los: writing a "1" to this bit extends the number of zeros at the input to 4096 bits, (approximately 2ms), before los is declared. r/w 0 0ict in-circuit-testing: writing a "1" to this bit causes all output pins to be in high impedance mode for in-circuit testing. the software ict function is equivalent to connecting pin 20 to ground. r/w 0 n ote : register type abrbreviation: r = read only, r/w = read or write, rur = reset upon read
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 27 t able 12: c hannel s tatus r egister c hannel s tatus r egister p arallel p ort a ddress c hannel 0: 0010 p arallel p ort a ddress c hannel 1: 0101 p arallel p ort a ddress c hannel 2: 1000 p arallel p ort a ddress c hannel 3: 1011 b it n o .s ymbol f unction r egister t ype r eset v alue 7dmon driver monitor output: this bit is set to a "1" to indicate current dmo is detected. any change in the state of this bit causes an interrupt to be generated. reading this register bit does not clear the dmo bit. r0 6losn loss of signal: this bit is set to a "1" to indicate current los condition is detected. any change in the state of this bit causes an interrupt to be generated. reading this register bit does not clear the los bit. r0 5 lcvn line code violation: this bit is set to a "1" to indicate current lcv condition is detected. any change in the state of this bit causes an interrupt to be generated. reading this register bit does not clear the lcv bit. r0 4tckln transmit clock loss: this bit is set to a "1" to indicate current txclk clock loss is detected. any change in the state of this bit causes an interrupt to be generated. reading this register bit does not clear the tckl bit. r0 3dmonis driver monitor output: this bit is set to a "1" every time the state of dmo status changes since last read. this bit is cleared by a read operation. rur 0 2losnis latched- loss of signal: this bit is set to a "1" every time the state of los changes since last read. this bit is cleared by a read operation. rur 0 1lcvnis latched- line code violation: this bit is set to a "1" every time the state of lcv changes since last read. this bit is cleared by a read operation. rur 0 0tclknis latched-transmit clock loss. this bit is set to a "1" every time the state of tckl changes since last read. this bit is cleared by a read operation. rur 0 n ote : n = channel number 0 to 3. n ote : register type abrbreviation: r = read only, r/w = read or write, rur = reset upon read
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 28 t able 13: c hannel m ask r egister c hannel m ask r egister p arallel p ort a ddress c hannel 0: 0011 p arallel p ort a ddress c hannel 1: 0110 p arallel p ort a ddress c hannel 2: 1001 p arallel p ort a ddress c hannel 3: 1100 b it n o .n ame f unction r egister t ype r eset v alue 7 -- this bit is reserved. r/w 0 6 -- this bit is reserved. r/w 0 5 -- this bit is reserved. r/w 0 4 -- this bit is reserved. r/w 0 3dmonis driver monitor output interrupt status: writing a "1" to this bit enables dmo alarm interrupt gener- ation. r/w 0 2losnis loss of signal interrupt status: writing a "1" to this bit enables los alarm interrupt gener- ation. r/w 0 1lcvnis line code violation interrupt status: writing a "1" to this bit enables lcv interrupt generation. r/w 0 0tcklnis transmit clock loss interrupt status: writing a "1" to this bit enables txclk clock loss interrupt generation. r/w 0 n ote : n = channel number 0 to 3. n ote : register type abrbreviation: r = read only, r/w = read or write, rur = reset upon read
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 29 t able 14: c hannel c ontrol r egister c hannel c ontrol r egister parallel port address channel 0: 0100 parallel port address channel 1: 0111 parallel port address channel 2: 1010 parallel port address channel 3: 1101 b it n o .s ymbol f unction r egister t ype r eset v alue 7 6 5 **** these bits are reserved. r/w r/w r/w 0 0 0 4lloopn local loop-back: writing a "1" to this bit enables analog local loop-back. simultaneously setting rloop high is not allowed. r/w 0 3 dloopn digital loop-back: writing a "1" to this bit enables digital loop-back. r/w 0 2 rloopn remote loop-back: writing a "1" to this bit enables remote loop-back. simultaneously setting lloop high is not allowed. r/w 0 1taosn transmit all ones: writing a "1" to this bit enables the all ones ami signal to be transmitted to the line. r/w 0 0txoffn transmitter off: writing a "1" to this bit powers down the transmitter and places the corresponding output driver in a high imped- ance mode. r/w 0 n ote : n = channel number 0 to 3. n ote : register type abrbreviation: r = read only, r/w = read or write, rur = reset upon read
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 30 microprocessor interface i/0 timing intel interface timing the signals used for the intel microprocessor inter- face are: address latch enable (ale), read enable (rd ), write enable (wr ), chip select (cs ), address and data bits. the microprocessor interface uses minimum external glue logic and is compatible with the timings of the 8051 or 80c188 with an 8-16 mhz clock frequency, and with the timings of x86 or i960 family or microprocessors. the interface timing shown in figure 17 and figure 18 is described in table 15. f igure 17. i ntel i nterface t iming (r ead ) ale_as rd_ds a[8:0] cs d[7:0] rdy_dtck not valid valid address of target register wr_r/w t64 t65 t67 t68 t66 t70 t69 t701 f igure 18. i ntel i nterface t iming (w rite ) ale_as a[8:0] cs d[7:0] wr_r/w data to be written address of target register rd_ds t64 t65 t71 t72 t73 t66 t770
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 31 t able 15: i ntel i nterface t iming s pecifications symbol p arameter m in t yp m ax c ondition t 64 a8 - a0 setup time to ale_as low 4ns t 65 a8 - a0 hold time from ale_as low. 2ns intel type read operation t 66 rds_ds pulse width 260 ns t 67 data valid from rds_ds* low. 240 ns t 68 data bus floating from rds_ds* high 2ns t 69 ale to rd time 4ns t 701 rd time to "not ready" (e.g., rdy_dtck toggling "low") 145 ns t 76 minimum time between read burst access (e.g., the rising edge of rd to falling edge of rd ) 60 ns intel type write operations t 71 data setup time to wr _r/w high 160 ns t 72 data hold time from wr _r/w high 0ns t 73 high time between reads and/ or writes 60 ns t 74 ale to wr time 4ns t 77 min time between write burst access (e.g., the rising edge of wr to the falling edge of wr ) 60 ns t 770 cs assertion to falling edge of wr _r/w 20 ns
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 32 motorola interface timing the signals used in the motorola microprocessor in- terface mode are: address strobe (as), data strobe (ds ), read/write enable (r/w ), chip select (cs ), address and data bits. the interface is compatible with the timing of a motorola 68000 microprocessor family with up to 16.67 mhz clock frequency. the in- terface timing is shown in figure 19, figure 20 and figure 21. the i/o specifications are shown in table 16. f igure 19. m icroprocessor i nterface t iming - m otorola t ype p rogrammed i/o r ead o peration wr_rw ale_as rd_ds a[8:0] cs d[7:0] rdy_dtck not valid valid data address of target register t78 t79 t80 f igure 20. m icroprocessor i nterface t iming - m otorola t ype p rogrammed i/o w rite o peration ale_as a[8:0] cs d[7:0] rd_ds rdy_dtck data to be written address of target register wr_rw t78 t82 t81
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 33 . f igure 21. m icroprocessor i nterface t iming - r eset p ulse w idth reset t90 t able 16: m otorola i nterface t iming s pecification s ymbol p arameter m in t yp m ax u nits microprocessor interface - motorola read operations (see figure 19) t 78 a3 - a0 setup time to falling edge of ale_as 5 ns t 79 rising edge of rd _ds to rising edge of rdy_dtck delay 0 ns t 80 rising edge of rdy_dtck to tri-state of d[7:0] 0 ns microprocessor interface - motorola write operations (see figure 20) t 78 a3 - a0 setup time to falling edge of ale_as 5 ns t 81 d[7:0] setup time to falling edge of rd _ds 10 ns t 82 rising edge of rd _ds to rising edge of rdy_dtck delay 0 ns reset pulse width - both motorola and intel operations (see figure 21) t 90 reset pulse width 30 ns
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 34 jitter tolerance input jitter tolerance measurements are presented for the following two situations. 1. the jitter attenuator within the channel-under- test is disabled. 2. the jitter attenuator within the channel-under- test is enabled and configured to operate in the re- ceive path. the results of the input jitter tolerance measure- ments are plotted in figure 22. test conditions ? test pattern 2^ 15 -1 ? (-6db) cable loss f igure 22. r eceive m aximum j itter t olerance 10 0 10 1 10 2 10 3 10 4 10 5 10 ?1 10 0 10 1 10 2 10 3 (freq.(mhz)) input jitter (uip?p) jat disabled itu-t g.823 mask jat 64bits jat 32bits 100 1000 10 .1 1
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 35 receiver jitter transfer function (jitter attenua- tor disabled) test conditions: ? test pattern 2^ 15 -1 - input jitter 0.5uip-pthe results of the input jitter tolerance measurements with the jitter attenuator enabled and configured to operate in the receive path are plotted in figure 23. receiver jitter transfer function (jitter attenua- tor enabled) test conditions: ? test pattern 2^ 15 -1 ? input jitter 75% of maximum jitter tolerance f igure 23. r eceiver j itter t ransfer f unction (j itter a ttenuator disabled ) 10 2 10 3 10 4 10 5 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 (freq.(mhz)) 20log(jout/jin) (db) xrt82l24a g.735-g739 specification performance f igure 24. j itter a ttenuation f unction 10 0 10 1 10 2 10 3 10 4 10 5 ?60 ?50 ?40 ?30 ?20 ?10 0 10 (freq.(mhz)) jitter attenuation (db) xrt82l24a performance itu.g.736 mask
xrt82l24a ? ? ? ? quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 36 ordering information p art n umber p ackage o perating t emperature r ange XRT82L24AIV 100 lead tqfp (14 x 14 x 1.4mm) -40 c to +85 c p ackage d issipation theta-ja 38 c/w theta-jc 6 c/w package dimensions 100 lead tqfp 14x14mm 75 51 50 26 125 76 100 d d 1 d d 1 b e a 2 a a 1 a seating plane l c n ote : the control dimension is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a 1 0.002 0.006 0.05 0.15 a 2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.622 0.638 15.80 16.20 d 1 0.547 0.555 13.90 14.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 a 0 7 0 7
? ? ? ? xrt82l24a quad e1 line transceiver with clock recovery and jitter attenuator rev. 1.1.2 37 notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no represen- tation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a users specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys- tem or to significantly affect its safety or effectiveness. products are not authorized for use in such applica- tions unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corpo- ration is adequately protected under the circumstances. copyright 2004 exar corporation datasheet august 2004. reproduction, in part or whole, without the prior written consent of exar corporation is prohibited. revision history r evision d ate d escription 1.0.0 11/02 initial issue 1.1.0 10/03 table 8 corrected pclk frequency from 33mhz to16mhz and changed pulled down to pulled up. figures 12 & 13 transformer ratio on receive side changed from 2:1 to 1:2. 1.1.1 06/04 added the manufacturing mark on the package drawing. 1.1.2 07/04 changed max power consumption for 100% mark density to 680 and 600 mw respectively for 75 and 120 ohm loads.
xrt82l24a -quad e1 line transceiver with ja & cdr home news careers investor relations contact us partnernet login search communications interface power management support info request how to order samples how to buy design technical documentation technical faqs product finder product tree technical support packaging evaluation boards cross references product change notifications obsolescence communications brochure storage brochure ibis models bsdl quality and reliability xrt82l24a print this page quad e1 line transceiver with ja & cdr features l on-chip clock recovery circuit l receive input can be transformer, or capacitor coupled l tri-state transmit output capacity l on-chip per channel driver failure monitoring circuit l pb-free, rohs compliant versions offered applications l digital access cross-connects (dacs) l channel banks l high-speed data transmission line cards l e1 multiplexer l public switching systems and pbx interfaces description demand for greater transmission capacity has propelled telecommunications, and networking system companies to develop more e1 (2.048 mbps) solutions. as more companies standardize on wide area network (wan) based, e1 transmission rates, or higher, companies are increasingly seeking off-the-shelf industry-proven components. exar's four-channel liu and framer are ideally suited for this growing e1 market. these devices are primarily targeted at single-channel and multi- channel e1 applications, such as telecommunications equipment, network multiplexers, central office switches and digital cross connects. in instances where clock recovery and jitter attenuation functions have moved from the asic to the transceiver, these new four-channel parts are ideal. the xrt82l24 is a fully-integrated, four-channel, short-haul line interface transceiver for 75? or 120? applications. each channel consists of a receiver, and a transmitter which accepts a single, or dual-rail digital input for signal transmission. it also includes a crystal-less jitter attenuator which can be selected in the transmit, or receive path through the host, or hardware mode. in addition, the device has high immunity to receiver interference, a per- channel transmit power shut-down capability, and meets or exceeds specifications no. ofch 4 datarate(s) e1 clk rec yes sh/lh s temp.range ind. oppwr sup/max cur 3.3v 5%, 228ma pkgs tqfp-100 documents datasheets datasheet version 1.1.2 august 2004 459.57 kb application notes tan-058, ds-1/e1 gr-1089 surge protection version 1.0.1 september 2006 69.43 kb tan-200, exar apis - os portability version 1.0.0 august 2007 88.46 kb http://www.exar.com/common/content/productdetails.aspx?id=162&parentid=3 (1 of 2) [31-jul-09 10:45:49 am]
xrt82l24a -quad e1 line transceiver with ja & cdr quality & reliability homepage material declaration sheets quality manual quarterly quality & reliability report rohs-green solutions industry specifications: itu g.703, g. 775, g.736 and g.823, and etsi 300-166. part number pkg code rohs min temp. (c) max temp. (c) status buy now order samples XRT82L24AIV-f lqfp100 -40 85 active XRT82L24AIV lqfp100 -40 85 active ? 2000-2009 exar corporation, fremont california, u.s.a. terms of use | site map http://www.exar.com/common/content/productdetails.aspx?id=162&parentid=3 (2 of 2) [31-jul-09 10:45:49 am]

▲Up To Search▲

Price & Availability of XRT82L24AIV

	To Download XRT82L24AIV Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .